FIG. 1 depicts a system 100 comprising a host 110 and a Non-Volatile-Memory (NVM) data storage device 120 as known in the art. Data storage devices such as data cards, USB sticks or other storage devices usually integrate NVM data flash memory 130 and a controller 140 into a single package 120.
When connected to a host device 110, for example a personal or a laptop computer, communication between the data storage card and the host device commence. The controller 140 within the data storage device 120 manages data transfer between the host and the flash memory 130 by serving as a gateway in both data transfer directions by writing to and reading from flash memory 130. The data consists of user data and management data and files. Management files comprising addresses updates and files naming. The operating system that enables the communication between the host and the data storage device is DOS (Disk Operating System) based.
FIG. 2 schematically depicts the relevant elements of the host's file system as known in the art. It consists of Master Boot Record (MBR); Partition Boot Record (PBR); Folders information; and File Allocation Table (FAT). The MBR consist information regarding the data storage device including FAT location and size; and root directory location. Its location is always logic address 0 which is translated by the controller to a physical address in the memory die. Root directory is with constant table size, consisting 512 rows, each with a description of the files or folders existing in the disk. It includes name, size, first block location and type of file (file or directory).
FAT is located in the memory array 130 but is governed by the host 110. It is a computer file system architecture originally developed by Bill Gates and Marc McDonald. It is the primary file system for various operating systems including DR-DOS, OpenDOS, freeDOS, MS-DOS, OS/2(v1.1), and Microsoft Windows (up to Windows Me). For floppy disks (FAT12 and FAT16 without long filename support) FAT has been standardized as ECMA-107 and ISO/IEC 9293. The use of long filenames with FAT is patented in part. The FAT file system is supported by virtually all existing operating systems for personal computers. This makes it an ideal format for solid-state memory cards and a convenient way to share data between operating systems.
The FAT comprises the addresses of all blocks in the memory disk. FAT record may be composed of 16 bits, FAT 16 (FAT12 and FAT32 are also used), hence indicating on a maximum 216 address locations. Assuming a disk capacity is <2 GB (16 Gb), each address is with a maximal 217 (64 KB) chunk size. FAT is backed-up by having two copies at all times, FAT1 and FAT2. The disk size dedicated for FAT in case of 2 GB disk is 2×16×216=256 KB.
FIG. 3 schematically depicts an example of the sequence of events that takes place when read operation commence according to prior art. Upon power-up, and possibly connecting the memory card to the host or per user request to access the memory card, the MBR is addressed, the host generates a copy of the FAT in its memory and approaches to the root directory where information regarding the files is extracted (either located in the root folder itself, or more typically in a subfolder associated with the folder which appears in the root directory). Once the location of the first block of the requested file is identified, the rest of the blocks are sequentially pointed by the FAT. The FAT is owned by the controller and it uses logic addresses—the translation of the logic addresses to physical addresses is done by the controller that allocates both the data and the FAT in specific physical locations within the memory array.
The block size is typically determined by the host—with a minimum size such that the maximum number of blocks in the disk will not exceed 216=65,536 (assuming FAT16 is used).
The following section schematically depicts the association of FAT entries with physical blocks within the array as used by methods of the art. When the host 110 initiate the read sequence (addressing the MBR, root directory, etc . . . ), it also initiate routines to be executed by the controller 140, in which the required physical blocks are read using a logical address to physical address mapping table that exists in the controller (there is limited capacity of memory in the controller used for such purposes). Using adequate protocol (SD/MMC/USB etc . . . ), the controller enables instructions and data transfer between the host 110 and the memory die 130. In typical case 8 entries in the FAT may be mapped to single Erase Sector (ES)—a specific physical location in the memory array. Typically, for each Physical Sector (PS) in the memory array there is at least single spare ES that is left empty
The following section describes the process of user data writing into a flash as used by methods of the art. During write operation where for example a new picture or a file with size of for example 1 MB is to be written into the memory array 130 by host 110, the sequence of events is similar to the process described previously. The main difference is that the relevant files, root directory, FAT and data files are modified. Whenever new data is loaded, a new file entry is generated in one of the subfolders of the root directory. Subsequently, the FAT is updated as well by looking for free entries in the host and allocating them for the picture or file to be recorded on the memory die where blocks of typically 4 KB size may be pointed by the FAT entries (256 free entries for 1 MB file). Write command is sent to the controller instructing it to write the user data, followed by command to the controller to update the FAT entries as well. The update corresponds to re-mapping of the logical to physical address table which is carried out by the controller.
FAT is typically updated by regenerating it in different physical locations according to the new mapping table. The previous physical location where the old FAT was stored in the memory 130 is typically erased and serves as part of spare ES. In standard data cards, when the card is physically full, (that is: all its memory has already been used before, but logically has free memory used data that is designated as “deleted”) a new picture or a file is loaded by first deleting written erase sectors containing deleted pictures or files.
As implied from the above, the logical addresses that are pointed out in the FAT and root directory are typically linked to various physical locations which are changed in each data transfer. Yet, logical addresses of management files may be linked to the same physical location in more than one data transfer with a frequency that depends on various applications such as die size, controller's algorithm, etc. As a result, even for a single program operation of the data storage device, the associated management blocks (root directory, FAT, etc.) may endure larger number of program and erase cycles. For example, to completely fill once a data card of 128 MB such as camera data card, more than 40 pictures can be taken at different instances with a single programming sequence per each picture. The associated physical to logic mapping operation typically changes throughout these 40 sequences, yet, the same mapping of the management blocks may repeat itself.
To conclude, in prior art, standard data storage device must support a minimum of several program and erase cycles in order to enable the repeatable mapping between physical to logical addresses even when the data storage device is used for One Time Program (OTP) application. Flash dies are typically being specified by the maximum designated number of program and erase cycles which range between 5 and 100,000 cycles. Note that in data flash memories, program operation is carried out in page mode (0.5-4 KB) while erase operation is carried out in Erase Sector (ES) of 32-128 KB size. The controller manages the data in the flash using ES chunks. In typical operation mode, while new data is loaded, the FAT and folders data are modified and actually written to another location in the memory region before the old ones are erased. The “old” location is not necessarily deleted (erased) immediately. It is typical that spare erase sectors are available for the management operations that are carried out by the controller.
While OTP data card may consist data flash memory with multiple program and erase cycling capability, other technologies with program only (OTP) capability may be used to form OTP data card as well. The advantage of the OTP memory over flash memory is the significant reduced cost per bit. This is possible because manufacturing cost of a given memory density using OTP technology is˜×2 lower than standard data flash technology.
Among others, it is possible to use as an OTP technology the 4 bits per cell NROM technology which reduce processing cost significantly compared to the state of the art, NAND type, data flash memory which is based on 2 bit per cell Multi-Level-Cell (MLC) data flash or 1 bit per cell Single-Level-Cell (SLC) data flash. This advantage is furthermore emphasized as when considering low density memory dies (<2 Gb) for data storage devices, the most appealing approach using NAND data flash at 90 nm technology node and below is SLC. SLC NAND is superior over MLC NAND under the above mentioned circumstances as the design complexity associated with the periphery circuitry is much simpler and cost effective in terms of die size.
OTP memory based data storage cards may be used either in a single content loading sequence (i.e., the entire card capacity or part of it is loaded only once) or alternatively, in a multiple loading sequences where the management portion of the die is significantly extended to avoid remapping of the management files to the same physical addresses. For example, typical FAT area requires ˜256 KB memory size in standard data flash while in OTP memory it may consume the same memory size per each data transfer sequence, ˜10 MB assuming 40 pictures are taken at different sequences (40×256 KB). In typical data storage device with a 128 MB memory die capacity, it consumes ˜10% of the of the data card capacity.
U.S. Pat. No. 5,392,427 to Barrett, et al. entitled “System for updating data stored on a flash-erasable, programmable, read-only memory (FEPROM) based upon predetermined bit value of indicating pointers”; discloses a method and system for updating data stored on a computer storage device. The data is contained in records or entries. Each record or entry has a primary pointer and an indicator. The indicator initially has each bit set to a predefined bit value. When data is to be updated (and thus, the record or entry containing the data is to be superseded), at least one bit of the indicator is changed from the predefined bit value to another bit value to point to the new record or entry and to indicate that the data in the new record or entry is an update of the data in the superseded record or entry. This method and system are especially suitable to be used in a write-once computer storage device.
U.S. Pat. No. 5,568,634 to Gordons; entitled “Method of writing in a non-volatile memory, notably in a memory card employing memory allocation strategies on size and occupancy basis”; discloses a system for the management of non-volatile memories, wherein, to avoid losses of information during writing, the critical writing sequences are locked. A back-up information element is stored before the performance of the critical section. The lock is constituted by the bits of the allocation table that designate the location of the saved back-up information. The lock is erased at the end of a normal writing sequence. If there is an abnormal interruption of a writing operation during the critical section, then the lock remains locked. This is detected when the power is turned on again, and the writing is resumed utilizing the saved information elements. The lock and the saved information elements are in a variable zone of the memory, thus preventing memory fatigue in the event of intensive use. Furthermore, the management of the memory is original in that two different memory allocation strategies are used to enable the detection, by the allocation table, of the presence of an information element whose location is not known.
U.S. Pat. No. 5,630,093 to Holzhammer, et al. entitled “Disk emulation for a non-volatile semiconductor memory utilizing a mapping table”; discloses a non-volatile semiconductor memory that is erased in blocks. The non-volatile semiconductor memory includes an active block for storing first data and a reserve block for storing second data. The second data is a copy of the first data. The copy is made during a clean-up operation prior to erasure of the active block. The non-volatile semiconductor memory also includes a mapping table for mapping a logical address of an allocation unit to a physical address of a sector within the non-volatile semiconductor memory.
U.S. Pat. No. 6,256,642 to Krueger, et al. entitled “Method and system for file system management using a flash-erasable, programmable, read-only memory”; discloses a method and system for memory management of a block-erasable Flash-EPROM. The system comprises a FEPROM manager and a file system. The FEPROM manager manages memory allocation and de-allocation of the FEPROM. The file system is a hierarchical directory system and uses the FEPROM manager to allocate and de-allocate memory. In a preferred embodiment, the FEPROM manager of the present invention provides for allocation of free space, de-allocation of allocated space, and reclamation of de-allocated space in a block-erasable FEPROM. Each block of the FEPROM contains a block allocation structure, data regions, and free space. The block allocation structure contains an allocation array which describes the allocation of the data region.
United States Patent Application 20030204659; to Huang, Kan-Chuan; entitled “Digital storage media with one-time programmable read only memory”; discloses a digital storage media connects to an electronic device for storing digital data transmitted from the electronic device. The digital storage media includes an interface control circuit for controlling interface between the electronic device and the digital storage media, a first memory for storing program codes of the digital storage media, and a second memory for storing digital data transmitted from the electronic device. The digital storage media also includes a memory control circuit electrically connected between the interface control circuit and the second memory for storing the digital data transmitted from the interface control circuit into the second memory, and a processor for controlling operations of the digital storage media. For storing the digital data transmitted from the electronic device, the second memory has metal-insulator-semiconductor transistors.
United States Patent Application 20070208908; to Moore; Christopher S.; et al.; entitled “Method and apparatus for using a one-time or few-time programmable memory with a host device designed for erasable/rewriteable memory”; discloses a method that can be used to enable one-time or few-time programmable memories to work with existing consumer electronic devices (such as those that work with flash erasable, non-volatile memory) without requiring a firmware upgrade, thereby providing backwards compatibility while minimizing user impact. As such, these embodiments are a viable way to bridge one-time or few-time programmable memories with existing consumer electronic devices that have flash card slots. These embodiments also allow future consumer electronic devices to be designed without updating firmware to include a file system customized for a one-time or few-time programmable memory.
U.S. Pat. No. 6,836,834; to Schulze, et al.; entitled “Memory card having one-time programmable memory”; discloses a memory card having a one-time programmable memory which stores a plurality of storage allocation tables and which is compatible with a host device. Details of memory card construction and operation can be found there.
NROM cells are described in many patents including U.S. Pat. No. 6,649,972 where NROM technology employs a virtual-ground array architecture with a dense crisscrossing of word lines and bit lines.
U.S. Pat. No. 7,4059,69 refers to standard Single-Level Cell (SLC) Nitride Read Only Memory (NROM) and Multi-Level Cell (MLC) NROM. The patent entitled “Non-volatile memory cell and non-volatile memory devices”; to Eitan, Boaz; discloses a non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a nonconducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device.
United States Patent Application 20060084219; to Lusky.; et al.; entitled “Advanced NROM structure and method of fabrication”; discloses a method to enable manufacturing the dual memory NROM memory die.